1. Field of the Invention
This invention relates to a magnetic memory device and a method of manufacturing the magnetic memory device. More specifically, this invention relates to an MRAM (Magnetic Random Access Memory) using an MTJ (Magnetic Tunnel Junction) structure as memory element devices.
2. Description of the Related Art
A magnetic memory device using tunneling magneto resistive effect (hereinafter, abbreviated as TMR), so called MRAM, has been proposed (see, for example, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell,” ISSCC 2000 Technical Digest, p. 128).
FIG. 49 shows the basic configuration of a conventional MRAM. As shown in FIG. 49, a plurality of isolations 102 with an STI (Shallow Trench Isolation) structure are formed in the surface of a p-type semiconductor substrate (or, well region) 101. In each device region excluding the regions of isolations, a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 103a, 103b are provided. Specifically, in the surface of the p-type semi-conductor substrate 101 corresponding to each device region demarcated by the plurality of isolations 102, for example, a plurality of n-type diffused layers 104a, 104b are selectively formed. On the surface of each p-type semiconductor substrate 101 between the plurality of diffused layers 104a, 104b, gate electrodes 105a, 105b are provided through a gate oxide film.
On the p-type semiconductor substrate 101, an insulator film 106 is provided. In the insulator film 106, for example, a plurality of wiring lines in a first level 107 to a fifth level 111 are formed. In this example, wiring lines 107a, 107b, 107c, 107d, 107e, 107f, 107g are provided in the first level 107. In the second level 108, wiring lines 108a, 108b, 108c, 108d, 108e, 108f, 108g are provided. In the third level 109, wiring lines 109a, 109b, 109c, 109d, 109e, 109f, 109g are provided. In the fourth level 110, wiring lines 110a, 110b are provided. In the fifth level 111, wiring lines 111a, 111b, 111c, 111d are provided.
Furthermore, in the insulator film 106, for example, there are provided first contact plugs 112a, 112c, 112e, 112g which connect the plurality of diffused levels 104a, 104b with each one of the wiring lines 107a, 107c, 107e, 107g in the first level 107. In addition, for example, there are provided second contact plugs 113a, 113c, 113e, 113g which connect the wiring lines 107a, 107c, 107e, 107g in the first level 107 with the wiring lines 108a, 108c, 108e, 108g in the second level 108, respectively. Moreover, for example, there are provided third contact plugs 114a, 114c, 114e, 114g which connect the wiring lines 108a, 108c, 108e, 108g in the second level 108 with the wiring lines 109a, 109c, 109e, 109g in the third level, respectively. Furthermore, for example, there are provided fourth contact plugs 115a, 115c which connect the wiring lines 109a, 109c in the third level 109 with the wiring lines 110a, 10b in the fourth level, respectively, and fourth contact plugs 115e, 115g which connect the wiring lines 109e, 109g in the third level 109 with the wiring lines 111b, 111d in the fifth level, respectively. In addition, for example, the wiring lines 110a, 110b in the fourth level 110 are connected with the wiring line 111a in the fifth level 111 via TMR element devices 116a, 116b. 
The MRAM with such a configuration comprises a memory cell and a core peripheral circuit for controlling the memory cell. In the memory cell, the wiring line 111a in the fifth level 111 connected to the TMR element devices 116a, 116b functions as a bit line. The wiring lines 109b, 109d in the third level 109 not connected to any one of wiring lines 110a, 110b in the fourth level 110 function as write word lines. The write word lines 109b, 109d are arranged so as to be perpendicular to the bit line 111a. The TMR element devices 116a, 116b, which are placed at the inter-sections of the bit line 111a and the write word lines 109b, 109d, are used as memory element devices. The MOSFET 103a, which is connected electrically to the TMR element devices 116a, 116b, functions as a switching element device. The gate electrode 105a of the MOSFET 103a functions as a read word line.
FIG. 50 shows an equivalent circuit of the memory cell (MRAM cell) with the above configuration. As shown in FIG. 50, the bit line 111a, is arranged to cross the write word line 109b (or 109d) and read word line 105a perpendicularly. At the intersection of the bit line 111a and the write word line 109b (or 109d), the TMR element device 116a (or 116b) is placed. One end of the TMR element device 116a (or 116b) is connected to the bit line 111a and the other end of the TMR element device 116a is connected to the MOSFET 103a. The gate electrode 105a of the MOSFET 103a serves as the read word line.
FIG. 51 shows an example of the configuration of the TMR element devices 116a, 116b. Each of the TMR element devices 116a, 116b has a three-layered structure composed of two magnetic layers and a nonmagnetic layer sandwiched between the two layers. Specifically, each of the TMR element devices 116a, 116b is configured in such a manner that, for example, a fixed magnetic layer (magnetic layer) 116-1, a tunnel junction layer (nonmagnetic layer) 116-2, and a magnetic recording layer (magnetic layer) 116-3 are stacked one on top of another in that order.
The fixed magnetic layer 116-1, which is composed of an antiferromagnetic layer and a ferromagnetic layer, is called a pin layer since the direction of magnetization is fixed in one direction. In contrast, the magnetic recording layer 116-3, which is composed of a ferromagnetic layer, is called a memory layer for storing data since the direction of magnetization can be changed freely. The direction of magnetization in the magnetic recording layer 116-3 can be changed by a combined magnetic field (current magnetic field) produced by the current flowing through the bit line 111a and the current flowing thorough the write word lines 109b, 109d. 
The operation of writing data into or reading data from an MRAM cell with such a configuration will be explained briefly. For example, to write data “1” or “0” into the TMR element device 116a, the write word line 109b and bit line 111a are selected first. Current (write current) is caused to flow through the selected write word line 109b and bit line 111a, thereby generating a current magnetic field. Then, only the magnetic field applied to the selected cell (TMR element device 116a) located at the intersection of the selected write word line 109b and bit line 111a exceeds the inversion threshold of magnetization in the TMR element device 116a. As a result, data is written into the TMR element device 116a. 
At this time, for example, when the direction of magnetization in the fined magnetic layer 116-1 and that in the magnetic recording layer 116-3 are parallel to each other in the same direction, the tunnel resistance sensed by current flow through the tunnel junction layer 116-2 becomes the lowest. In this state, “1” can be stored. In contrast, when the direction of magnetization in the fixed magnetic layer 116-1 and that in the magnetic recording layer 116-3 are parallel to each other in opposite directions, the tunnel resistance sensed by current flow through the tunnel junction layer 116-2 becomes the highest. In this state, “0” can be stored. That is, in the MRAM, the difference in tunnel resistance is stored in the form of data “1” or “0.”
On the other hand, to read data “1” or “0” written in the TMR element device 116a, the read word line 105a and bit line 111a are selected first. Then, current flows from the bit line 111a to the ground (Gnd) line through the TMR element device 116a and MOSFET 103a. The difference in the current flowing in the Gnd line is read as the difference in the tunnel resistance by the core peripheral circuit, thereby determining the data (“1” or “0”) in the TMR element device 116a. 
In the MRAM with the above configuration, to decrease the write current, it is desirable that the bit line 111a should be provided as close to the write word lines 109b, 109d as possible.
However, in the conventional MRAM having the aforementioned memory cell, the core peripheral circuit for controlling the memory cell is provided around the memory cell. The core peripheral circuit is generally formed by the same process with the memory cell from the viewpoint of cost performance. Therefore, arranging the bit line 111a and the write word lines 109b, 109d close to one another inevitably causes the wiring line 109f in the fourth level 109 and the wiring line 111c in the fifth level 111 in the core peripheral circuit to be provided close to each other.
However, when a plurality of wiring lines are arranged close to one another, inductance components are liable to induce. Particularly when two wiring lines arranged very close to each other are used in the core peripheral circuit, current flow in one wiring line can generate electromotive force on the other wiring line, which may cause a problem. Specifically, in the future, the bit line 111a and the write word lines 109b, 109d will possibly get closer and closer to one another. In that case, the wiring line 109f in the third level 109 and the wiring line 111c in the fifth level 111 will get very close to each other in the core peripheral circuit, with the result that the induction of inductance components will become a serious problem. The inductance components are expected to become still greater, when yoke wiring lines are used.
As described above, in the conventional MRAM, when the bit line and the word lines are arranged closely one another to decrease the write current, this causes the wiring lines in the core peripheral circuit to get closer to one another, which can permit inductance components to induce. There is a possibility that interference caused by electromotive force between wiring lines arranged closely one another will become a problem.